From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,INVALID_MSGID autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 103376,8c8bbb1419c8e81a X-Google-Attributes: gid103376,public From: kenner@lab.ultra.nyu.edu (Richard Kenner) Subject: Re: Waiver question Date: 1997/04/29 Message-ID: <5k52k2$7v0$1@news.nyu.edu>#1/1 X-Deja-AN: 238297491 References: <1997Apr28.151327.1@eisner> Organization: New York University Ultracomputer Research Lab Newsgroups: comp.lang.ada Date: 1997-04-29T00:00:00+00:00 List-Id: In article <1997Apr28.151327.1@eisner> kilgallen@eisner.decus.org (Larry Kilgallen) writes: >The minimum addressable unit on DEC Alpha is 32 bits, except for the very >latest chip where it was altered for purposes of Intel emulation. GNAT >reportedly "does" DEC Alpha, and I presume that is without relying on >OS traps for every unaligned instruction :-). This is quite confused. The Alpha was very carefully designed with a set of instructions whose purpose is to allow efficient loading and storing of 8- and 16-bit objects. DEC has a nice explanation of these sequences someplace on their web pages (sorry, but I can't find my pointer to it at the moment). The problem with these sequences is that they are not atomic. That is that problem that will be remedied on Alpha processors starting with EV56.