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From: pbgraham@engin.umich.edu (Paul B. Graham)
Subject: Re: ADA - VHDL
Date: 1996/07/12
Message-ID: <4s5jmg$47s@srvr1.engin.umich.edu>#1/1
X-Deja-AN: 167986508
references: <4s09jq$ddn@srvr1.engin.umich.edu> <4s0m0dINNgbh@maz4.sma.ch>
 <31E4E37A.4487EB71@sh.bel.alcatel.be>
organization: University of Michigan Engineering, Ann Arbor
newsgroups: comp.lang.ada,comp.lang.vhdl
Date: 1996-07-12T00:00:00+00:00
List-Id: <comp.lang.ada>



> >    for i in reverse Weekdays loop
> 
> There exist an attribute 'reverse_range
> which can be used to get the same result.

Actually not.  The 'RANGE and 'REVERSE_RANGE attributes in VHDL can only
be used with array types.  Thus in Ada you can write

    for i in character loop ...
or
    for i in reverse character loop ...

But in VHDL you must do

    for i in character loop
or
    for i in character'high downto character'low loop

because the construct

    for i in character'reverse_range loop

is illegal.

Paul