From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM autolearn=ham autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 103376,54889de51045a215 X-Google-Attributes: gid103376,public X-Google-ArrivalTime: 2003-10-16 17:26:36 PST Path: archiver1.google.com!news1.google.com!newsfeed.stanford.edu!headwall.stanford.edu!newshub.sdsu.edu!elnk-nf2-pas!newsfeed.earthlink.net!wn14feed!wn13feed!worldnet.att.net!204.127.198.203!attbi_feed3!attbi_feed4!attbi.com!rwcrnsc52.ops.asp.att.net.POSTED!not-for-mail Message-ID: <3F8F372D.9040801@comcast.net> From: "Robert I. Eachus" User-Agent: Mozilla/5.0 (Windows; U; Windows NT 5.0; en-US; rv:1.0.2) Gecko/20021120 Netscape/7.01 X-Accept-Language: en-us, en MIME-Version: 1.0 Newsgroups: comp.lang.ada Subject: Re: += in ada References: <3F7316F7.219F@mail.ru> <17cd177c.0310010606.52da88f3@posting.google.com> <3F8BC74F.2CFBFF37@0.0> <1066312000.671303@master.nyc.kbcfp.com> <1066322883.139702@master.nyc.kbcfp.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit NNTP-Posting-Host: 24.34.139.183 X-Complaints-To: abuse@comcast.net X-Trace: rwcrnsc52.ops.asp.att.net 1066350395 24.34.139.183 (Fri, 17 Oct 2003 00:26:35 GMT) NNTP-Posting-Date: Fri, 17 Oct 2003 00:26:35 GMT Organization: Comcast Online Date: Fri, 17 Oct 2003 00:26:35 GMT Xref: archiver1.google.com comp.lang.ada:1031 Date: 2003-10-17T00:26:35+00:00 List-Id: Hyman Rosen wrote: > In C++, I can say A += B, and then I don't need the temporary. If I say > A = B + C, then I do. But Ada forces you to say A = A + b for the first > case, and that gives you the temporary that you don't need. Which makes Ada better for most common CPUs today, right? In a processor with register renaming and OoO execution, which all Pentiums since the Pentium Pro and all Celerons, Athlons, and Durons have, register pressure can be caused by a lack of register names, but not registers. So in (pseudo)code like load R1,A add R1,B store R1,A the CPU will actually use a pair of renaming registers to represent R1 in this code fragment. And no matter whether you use the "Ada" approach or the "C++" approach to defining the sequence, you will still use two renaming registers and one register name to implement the code. (Oh, and the time to execute the code will probably be dominated by the time to fetch A and B if they are not already in registers or L1 cache.) Modern CPUs are so far from the finite state machines you may have been taught about in some Assembler class that it isn't even funny. I usually say that modern processors have lots of circutry devoted to confusing anyone who tries to debug software using a debugger. The problem is not just that the states you see in the debugger don't exist when your code is running normally, no states corresponding to the ISA exist when the processor is running normally. In fact, no states at all exist when the processor is running. If you tell the processor to create some sort of a state and push it on the stack it will do that. Just remember that the state you see was manufactured this way because you asked the processor to do so. -- Robert I. Eachus "Quality is the Buddha. Quality is scientific reality. Quality is the goal of Art. It remains to work these concepts into a practical, down-to-earth context, and for this there is nothing more practical or down-to-earth than what I have been talking about all along...the repair of an old motorcycle." -- from Zen and the Art of Motorcycle Maintenance by Robert Pirsig