From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-0.3 required=5.0 tests=BAYES_00, REPLYTO_WITHOUT_TO_CC autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 103376,5a97e6705e234408 X-Google-Attributes: gid103376,public X-Google-ArrivalTime: 2001-09-19 17:43:32 PST Path: archiver1.google.com!newsfeed.google.com!newsfeed.stanford.edu!news-spur1.maxwell.syr.edu!news.maxwell.syr.edu!cpk-news-hub1.bbnplanet.com!news.gtei.net!yellow.newsread.com!bad-news.newsread.com!netaxs.com!newsread.com!POSTED.newshog.newsread.com!not-for-mail Message-ID: <3BA93BB1.3685D423@intercom.com> From: "David B. Littell" Reply-To: davidl@intercom.com X-Mailer: Mozilla 4.76 [en] (X11; U; FreeBSD 2.2.8-RELEASE i386) X-Accept-Language: en MIME-Version: 1.0 Newsgroups: comp.lang.ada Subject: Re: Expected bytes per sloc (semicolons) performance References: <8f23da36.0109181403.52128d70@posting.google.com> <_hRp7.7630$ot.1153235@typhoon.ne.mediaone.net> <5ee5b646.0109190213.1092dc91@posting.google.com> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Date: Thu, 20 Sep 2001 00:43:31 GMT NNTP-Posting-Host: 64.105.16.43 X-Complaints-To: Abuse Role , We Care X-Trace: newshog.newsread.com 1000946611 64.105.16.43 (Wed, 19 Sep 2001 20:43:31 EDT) NNTP-Posting-Date: Wed, 19 Sep 2001 20:43:31 EDT Organization: Intercom Online (intercom.com) Xref: archiver1.google.com comp.lang.ada:13193 Date: 2001-09-20T00:43:31+00:00 List-Id: Robert Dewar wrote: > > "Jeff Creem" wrote in message news:<_hRp7.7630$ot.1153235@typhoon.ne.mediaone.net>... > > As for RISC/CISC.... One sometimes ends up with slightly larger code on a > > RISC than > > CISC machine but this probably has almost as much to do with mandatory nops, > > missed delayed branch opportunities and alignment requirements as it does > > with > > the straight RISC/CISC issues. > > This is a misleading assessment. First of all most modern > RISC machines do not have mandatory nops etc, so you are > really talking about old style architectures here. > Both MIPS (including MIPS32) and ARM processors provide a branch delay slot which may or may not be useful to the compiler. And the MIPS still has all those nasty pipeline hazards which definitely require nops to negate. I guess I'm not sure what a "modern" RISC is - each of the "big three" (MIPS, ARM, PowerPC) is haunted by legacy grodiness. This seems especially true of the MIPS - the canonical "drunken frat boy" 4th-year student project. ;-) Dave