From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,INVALID_MSGID autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 146b77,d275ffeffdf83655 X-Google-Attributes: gid146b77,public X-Google-Thread: 103376,d275ffeffdf83655 X-Google-Attributes: gid103376,public X-Google-Thread: 115aec,d275ffeffdf83655 X-Google-Attributes: gid115aec,public From: Ola Liljedahl Subject: Re: Ada vs C++ vs Java Date: 1999/01/27 Message-ID: <36AEDCEE.23964EF7@enea.se>#1/1 X-Deja-AN: 437466775 Content-Transfer-Encoding: 7bit References: <369C1F31.AE5AF7EF@concentric.net> <369DDDC3.FDE09999@sea.ericsson.se> <369e309a.32671759@news.demon.co.uk> <77ledn$eu7$1@remarQ.com> <77pnqc$cgi$1@newnews.global.net.uk> <8p64spq5lo5.fsf@Eng.Sun.COM> <782r25$k18$1@nnrp1.dejanews.com> To: robert_dewar@my-dejanews.com Content-Type: text/plain; charset=us-ascii Organization: Enea OSE Systems AB Mime-Version: 1.0 Newsgroups: comp.lang.ada,comp.vxworks,comp.realtime Date: 1999-01-27T00:00:00+00:00 List-Id: robert_dewar@my-dejanews.com wrote: > > > Assembly language is simpler than any high-order > > language, but it's lots more work to code in assembly. > > Now let me guess. The last time you looked at machine > language was in the 80's, right? Yes, in those days, the > semantics of machine language was pretty simple. > > I am afraid that things have changed. At this stage the > full execution semantics of a modern chip with extensive ^^^^^^^^^ > instruction-level parallelism is remarkably complex along > ALL the dimensions I mention above. A chip like the Pentium > II, if you include efficiency issues, which are indeed not > fully documented publicly, let alone formally specified, > you have something far MORE complicated than any of the > languages we are talking about here. Wrong. The semantics of the assembly level instructions is for all CPU architectures I know of (68K, SPARC, PowerPC) extremely simple. The semantics is that of a sequential execution of instructions where each instruction complete before the next is executed. That a particual implementation is actually pre-fetching instructions, using branch prediction, out of order issue and completion etc etc etc does NOT affect the semantics. All these implementation details ONLY affect the performance of the implementation, not the semantics. The only parts of the architecture/implementation that changes the semantics for these architectures is the delayed (imprecise) exceptions for floating point operations and the advanced memory models (Partial Store Order, Relaxed Memory Order) that some implementations might have. Ok, maybe I missed some other (minor) aspect, please correct me. -- Ola Liljedahl olli@enea.se