From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: * X-Spam-Status: No, score=1.6 required=5.0 tests=BAYES_05,INVALID_MSGID, REPLYTO_WITHOUT_TO_CC autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 115aec,5495dac456fa22ef X-Google-Attributes: gid115aec,public X-Google-Thread: f849b,167419cb5887cd4c X-Google-Attributes: gidf849b,public X-Google-Thread: 103376,5495dac456fa22ef X-Google-Attributes: gid103376,public From: Marin David Condic Subject: Re: Processor Synchronization Date: 1999/01/21 Message-ID: <36A73C17.64B2B79E@pwfl.com>#1/1 X-Deja-AN: 435231804 Content-Transfer-Encoding: 7bit Sender: condicma@bogon.pwfl.com References: <36A509DB.95F62C0B@pwfl.com> <36A51F3A.2207F91@west.raytheon.com> <36A602E0.DA6E298F@pwfl.com> <36A65D72.EDED6643@west.raytheon.com> Content-Type: text/plain; charset=us-ascii Organization: Pratt & Whitney Mime-Version: 1.0 Reply-To: diespammer@pwfl.com Newsgroups: comp.lang.ada,comp.realtime,comp.arch.embedded Date: 1999-01-21T00:00:00+00:00 List-Id: Ken Keys wrote: > I have never seen multiple processors coupled that closely. Usually, > processors are tied to some external event through interrupts or > whatever. Where the events themselves are unavailable, the input data > are given a timestamp that is referenced to some common clock--not > necessarily a time of day clock. Sometimes this timestamping requires > you to do some interpolation to get the data to line up as in, for > instance, the case of merging information from a Radar sensor with that > from an IR sensor where there are different amounts of processing delay > and differing update rates. Besides, if the data is coming from > something like a video raster, deciding just where in the elapsed time > covered by that raster the data occurs requires some interpretation. In this application, you wouldn't want to tie the processors together with a common interrupt or clock. That creates a single point failure and the reason for having the two processors is to minimize risk if something breaks. The reason for tightly aligning both channels is because you want them operating on essentially the same data at the same time so that if one goes down, the other takes over and there isn't a skipped beat. When we're reading A/Ds or F/Ds that are monitoring LVDTs or RVDTs or rotor speeds, data can get old very fast. Loop closure on stale data can get unstable. > > Are your processors in some kind of redundant voting arrangement where > they are executing the exact same code on the same inputs? If so, that > probably represents a fairly specialized case. You might be able to find > some information on that type of case in some NASA pubs. > The processors are doing exactly what you describe. As to how uncommon that is, I'm afraid I couldn't say. I know it is fairly common to go with dual redundant systems in a number of mission critical applications. The Ariane 5 disaster (please! not that again!) was an example of the dual redundancy not succeeding, but that hasn't stopped us from building them that way. I know that tight synchronization between two or more radios is another case. Your basic frequency hopping radio (cell phones and classified military stuff) have to agree pretty accurately on what time it is so that they can all change frequencies at the same time. (And that's just about all I want to say on *that* subject in a public forum!) It may be specialized enough that nobody has done any theoretical research into various algorithms. I may be SOL in hoping to find something like this. But it seemed like a good idea to ask and see what comes up. MDC -- Marin David Condic Real Time & Embedded Systems, Propulsion Systems Analysis United Technologies, Pratt & Whitney, Large Military Engines M/S 731-95, P.O.B. 109600, West Palm Beach, FL, 33410-9600 Ph: 561.796.8997 Fx: 561.796.4669 ***To reply, remove "bogon" from the domain name.*** "Airplanes are interesting toys but of no military value." -- Marechal Ferdinand Foch, Professor of Strategy, Ecole Superieure de Guerre.