From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: * X-Spam-Status: No, score=1.4 required=5.0 tests=BAYES_50,INVALID_MSGID autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 115aec,5495dac456fa22ef X-Google-Attributes: gid115aec,public X-Google-Thread: 103376,5495dac456fa22ef X-Google-Attributes: gid103376,public From: The Bohemian Monk Subject: Re: Processor Synchronization Date: 1999/01/21 Message-ID: <36A6DBB0.594A@wctc.net>#1/1 X-Deja-AN: 435110728 Content-Transfer-Encoding: 7bit References: <36A509DB.95F62C0B@pwfl.com> Content-Type: text/plain; charset=us-ascii Organization: Logic Weavers MIME-Version: 1.0 NNTP-Posting-Date: Wed, 20 Jan 1999 23:50:08 CDT Newsgroups: comp.lang.ada,comp.realtime Date: 1999-01-21T00:00:00+00:00 List-Id: After reading all the thread ... damn guys wake up. A processor as simple as the 8088 has bus sync signals to allow multiple processors on a single buss, or a single memory. Software does little for multiprocessing, hardware does the most, unless you program embedded in something like Forth. With non-buss-master processesors you can use a PAL to envoke wait-states based on buss signals, all in hardware with simple memory table semaphores for access control. ---------------------------------------------- Marin David Condic wrote: > > I am preparing an in-house class on embedded system executives and I > want to present a comprehensive overview of different designs. One of > the areas I want to cover is processor synchronization. I am looking for > a book or other reference material that discusses techniques for > synchronizing independent processors. Specifically, I am interested in > techniques used when building dual (or multiple) channel systems with > relatively primitive communication between the two channels. (discrete > lines, Manchester data link, etc.) Information pertaining to use of > operating systems (e.g. Unix) and distributed systems may be interesting > but not useful in this case. > > The most general description of the problem domain I can come up with is > this: The problem is at power-up, you have to get both processors > ticking off at the same "heartbeat" so that they have the same frame of > reference. Generally, you're going to have N cycles (frames, slots, > whatever your favorite terminology is) and it is important that both > processors be operating on cycle X at the same time. Once running, the > processors have to detect drift in their cycling and correct for this so > that they continue to both start on the same cycle at the same time. We > have done this sort of thing in-house, but I'm looking for a discussion > of a variety of algorithms and some analysis of the strengths & > weaknesses of each. > > If anybody has a favorite book, article or web-page on this subject, I > would appreciate hearing about it. Thanks. > > MDC > -- > Marin David Condic > Real Time & Embedded Systems, Propulsion Systems Analysis > United Technologies, Pratt & Whitney, Large Military Engines > M/S 731-95, P.O.B. 109600, West Palm Beach, FL, 33410-9600 > Ph: 561.796.8997 Fx: 561.796.4669 > ***To reply, remove "bogon" from the domain name.*** > > "Nobody shot me." > > -- Last words of Frank Gusenberg when asked by police who > shot him fourteen times with a machine gun in the Saint > Valentine's Day Massacre. -- _________________________________________________________ Christopher Passauer Logic Weavers Kerri Dean lgicwvrs@wctc.net 715\421-4305