From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=0.2 required=5.0 tests=BAYES_00,INVALID_MSGID, REPLYTO_WITHOUT_TO_CC autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 103376,3ccb707f4c91a5f2 X-Google-Attributes: gid103376,public From: "Norman H. Cohen" Subject: Re: Fast locking (Was Re: Java vs Ada 95) Date: 1996/11/11 Message-ID: <32877756.47F1@watson.ibm.com>#1/1 X-Deja-AN: 195825561 references: <325BC3B3.41C6@hso.link.com> <55gkch$gg6@fozzie.sun3.iaf.nl> <55o4g4$ki8@fozzie.sun3.iaf.nl> <1996Nov5.235745.1@eisner> <55r16k$m00@fozzie.sun3.iaf.nl> <1996Nov7.073254.1@eisner> content-type: text/plain; charset=us-ascii organization: IBM Thomas J. Watson Research Center mime-version: 1.0 reply-to: ncohen@watson.ibm.com newsgroups: comp.lang.ada x-mailer: Mozilla 3.0 (Win95; I) Date: 1996-11-11T00:00:00+00:00 List-Id: Robert Dewar wrote: > > Geert says > > "> I can't imagine there are many systems around these days that do not > > provide efficient test-and-set semantics. ... > > Your imagination is deficient. Examples are the RS6000 and all earlier > MIPS chips. There are others! The RS6000 is not a processor, but a family of systems, early versions of which were based on the POWER architecture and later versions of which were based on the PowerPC architecture. Robert is presumably referring to the POWER architecture, which did not include syncrhonization operations for shared-memory multiprocessors. In contrast, the PowerPC architecture provides the lwarx (load word arithmetic and reserve, indexed) and stwcx (store word conditional, indexed) instructions, which provide powerful and efficient syncrhonization. Every PowerPC architecture document I have seen includes an appendix with syncrhonization programming examples, showing how a handful of instructions, generally built around a lwarx/stwcx pair, can be used to program such syncrhonization idioms as Fetch-and-Store, Fetch-and-Add, Test-and-Set, Compare-and-Swap, and lock/unlock. (My favorite PowerPC syncrhonization instruction, used to ensure that out-of-order loads and stores do not violate the semantics of volatile variables and memory-mapped I/O ports, is Enforce In-Order Execution of I/O. Its mnemonic is, naturally, eieio.) -- Norman H. Cohen mailto:ncohen@watson.ibm.com http://www.research.ibm.com/people/n/ncohen