From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM autolearn=unavailable autolearn_force=no version=3.4.4 X-Received: by 10.98.6.3 with SMTP id 3mr690074pfg.15.1494268779015; Mon, 08 May 2017 11:39:39 -0700 (PDT) X-Received: by 10.157.14.91 with SMTP id n27mr1290835otd.8.1494268778954; Mon, 08 May 2017 11:39:38 -0700 (PDT) Path: eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c26no1532131itd.0!news-out.google.com!v18ni2179ita.0!nntp.google.com!c26no1532129itd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.ada Date: Mon, 8 May 2017 11:39:38 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:191:8303:2100:5985:2c17:9409:aa9c; posting-account=fdRd8woAAADTIlxCu9FgvDrUK4wPzvy3 NNTP-Posting-Host: 2601:191:8303:2100:5985:2c17:9409:aa9c References: <0fc56bf7-1cfa-4776-9c47-a573db315c5f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <29e2a3a3-326c-4a32-960a-2ef1ec5f9735@googlegroups.com> Subject: Re: Portable memory barrier? From: Robert Eachus Injection-Date: Mon, 08 May 2017 18:39:38 +0000 Content-Type: text/plain; charset=UTF-8 Xref: news.eternal-september.org comp.lang.ada:46706 Date: 2017-05-08T11:39:38-07:00 List-Id: On Monday, May 8, 2017 at 12:22:55 PM UTC-4, Dmitry A. Kazakov wrote: > On 2017-05-08 17:56, Robert Eachus wrote: > > One sentence summary: The CPU will play lots of tricks behind your > > back, but in such a way you can pretend your code works as you intended. > > (Er, after you get the bugs out.) > > > > On Monday, May 8, 2017 at 3:45:26 AM UTC-4, Dmitry A. Kazakov wrote: > > > >> I don't believe either of the sequences can get reordered by the CPU, > >> but it is only belief and common sense. > > > > Silly rabbit, Trix are for kids. Oops, silly programmer, common > > sense has nothing to do with modern CPUs. > [...] > > Is any of this important to a high-level language programmer? Not > > really, unless they are working in hard real time. (Which I did.) If you > > program in assembler, or more likely work on a compiler back-end, > > knowing which instructions fit together is important. Even more > > important is coding so that an instruction that references a new cache > > line in memory is followed by as many instructions as possible that > > don't use that value. Some times you run into cases where you want to > > take advantage of write combining or some other trick involving the > > write pipe--but today, smart compiler optimization is about accesses to > > main memory and not much else. > > I don't see anything there what would prevent CPU from changing the > order of accesses to two *independent* memory locations when only the > program logic ties them nothing else. Well, except that there is no > obvious reason why it would like to change that order. > > Wikipedia provides a more simple example of the problem: > > https://en.wikipedia.org/wiki/Memory_barrier > > The case of a lock-free FIFO is different because it involves index and > array element. > > For practical use when the buffer size is > 1 there cannot be any problem. > > Yet the question stands. In particular, which Ada primitives may ensure > safe implementations of lock-free structures when no protected objects used. > > -- > Regards, > Dmitry A. Kazakov > http://www.dmitry-kazakov.de