From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,LOTS_OF_MONEY autolearn=unavailable autolearn_force=no version=3.4.4 X-Received: by 2002:a24:3f4c:: with SMTP id d73-v6mr6953576ita.30.1530627598927; Tue, 03 Jul 2018 07:19:58 -0700 (PDT) X-Received: by 2002:aca:1a18:: with SMTP id a24-v6mr3565148oia.5.1530627598807; Tue, 03 Jul 2018 07:19:58 -0700 (PDT) Path: eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!news.uzoreto.com!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!u78-v6no679917itb.0!news-out.google.com!z3-v6ni848iti.0!nntp.google.com!u78-v6no679913itb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.ada Date: Tue, 3 Jul 2018 07:19:58 -0700 (PDT) In-Reply-To: <2ae5f66b-46ea-42d9-8af3-bacbaa60e03b@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=47.185.195.62; posting-account=zwxLlwoAAAChLBU7oraRzNDnqQYkYbpo NNTP-Posting-Host: 47.185.195.62 References: <2ae5f66b-46ea-42d9-8af3-bacbaa60e03b@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <1f05fffc-952d-440e-b59d-391edeac5b4f@googlegroups.com> Subject: Re: new DARPA initiative: optimizing compiler to logic-gates+PCB target From: "Dan'l Miller" Injection-Date: Tue, 03 Jul 2018 14:19:58 +0000 Content-Type: text/plain; charset="UTF-8" Xref: reader02.eternal-september.org comp.lang.ada:53534 Date: 2018-07-03T07:19:58-07:00 List-Id: On Monday, July 2, 2018 at 11:34:22 AM UTC-5, Shark8 wrote: > On Saturday, June 30, 2018 at 9:50:29 AM UTC-6, Dan'l Miller wrote: > > https://www.eetimes.com/document.asp?doc_id=1333422#msgs > > > > What the Electronics Resurgence Initiative (ERI) describes seems to be somewhere in the vicinity of Ada*+VHDL**+SPICE***+ATP****. > > > > * e.g., for at least algorithmic description and data-structure/record-layout description, and perhaps general front-end/optimizing-backend architecture of bringing the concepts of a software compiler to ASIC/FPGA+PCB hardware > > > > ** e.g., for digital-logic description > > > > *** e.g., for analog-electronics modeling, especially on the PCB > > > > **** e.g., automated theorem prover, for automated transformation in lifter, lateral, and lowering directions > > > > $100 million bet is on the table at the DARPA casino. > > > > (Around AD2000 or so give or take a few years, Shlaer-Mellor world thought this was going to be their space to dominate. Their vacuum/void is someone else's to fill nowadays.) > > Hm, this rather sounds a lot like my idea for a fully integrated HW/SW IDE. Yes, I think so. I share this with c.l.a to show how your idea is the dawn of a new era (and imperative-machine-code-only targets are so 20th-century).