From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,INVALID_DATE autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 103376,2d886a1f8c2fd7b X-Google-Attributes: gid103376,public X-Google-ArrivalTime: 1993-03-22 23:52:04 PST Newsgroups: comp.lang.ada Path: sparky!uunet!elroy.jpl.nasa.gov!swrinde!cs.utexas.edu!csc.ti.com!tilde.csc.ti.com!mksol!strohm From: strohm@mksol.dseg.ti.com (john r strohm) Subject: Re: How does Alsys index bit-arrays on Intel ? Message-ID: <1993Mar22.191652.16458@mksol.dseg.ti.com> Organization: Texas Instruments, Inc References: <1993Mar19.193443.524@scf.loral.com> Distribution: inet Date: Mon, 22 Mar 1993 19:16:52 GMT Date: 1993-03-22T19:16:52+00:00 List-Id: In article <1993Mar19.193443.524@scf.loral.com> bashford@srs.loral.com (Dave Bashford) writes: >Can anyone tell me definitively whether a packed array of bits is indexed >with the least-significant index in the most- or least-significant bit of >each byte on an Intel-targeted Alsys Ada compiler ? > >least-significant index in the least-significant bit: > 7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8,23,22,... >or least-significant index in the most-significant bit: > 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,... This comes up often enough that it is worth saying. ANSI/MIL-STD-1815A "Reference Manual for the Ada Programming Language" section 13.4 paragraph 5 contains the following sentence: "The ordering of bits in a storage unit is machine-dependent and may extend to adjacent storage units." The same pargraph also contains the following sentence: "Whether a component is allowed to overlap a storage boundary, and if so, how, is implementation-defined." In other words, different compilers for different target processors are allowed to do things differently.