From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00 autolearn=ham autolearn_force=no version=3.4.4 X-Google-Thread: 107079,9d9cef47f5d1976c X-Google-Thread: 103376,ec0aac9465177ad0 X-Google-Attributes: gid107079,gid103376,public X-Google-Language: ENGLISH,ASCII Path: g2news2.google.com!postnews.google.com!i3g2000cwc.googlegroups.com!not-for-mail From: "jimmaureenrogers@worldnet.att.net" Newsgroups: sci.math.num-analysis,comp.lang.ada Subject: Re: Multithreaded scientific programming Date: 6 Oct 2006 13:57:51 -0700 Organization: http://groups.google.com Message-ID: <1160168271.767578.81540@i3g2000cwc.googlegroups.com> References: <1159978124.458442.80520@m7g2000cwm.googlegroups.com> <4523e925$1@nntp.unige.ch> <1159998421.978196.161210@c28g2000cwb.googlegroups.com> <1160007272.875375.190830@b28g2000cwb.googlegroups.com> <7267657.YP3qbeQrCS@linux1.krischik.com> NNTP-Posting-Host: 209.194.156.4 Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable X-Trace: posting.google.com 1160168277 30718 127.0.0.1 (6 Oct 2006 20:57:57 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Fri, 6 Oct 2006 20:57:57 +0000 (UTC) User-Agent: G2/1.0 X-HTTP-UserAgent: Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.0; InfoPath.1; .NET CLR 1.1.4322),gzip(gfe),gzip(gfe) Complaints-To: groups-abuse@google.com Injection-Info: i3g2000cwc.googlegroups.com; posting-host=209.194.156.4; posting-account=SqOfxAwAAAAkL81YAPGH1JdBwpUXw9ZG Xref: g2news2.google.com sci.math.num-analysis:6323 comp.lang.ada:6895 Date: 2006-10-06T13:57:51-07:00 List-Id: Bj=F6rn Persson wrote: > Martin Krischik wrote: > > David B. Chorlian wrote: > >> Talk about cache, TLB, and other memory management topics which > >> are the serious problems in large-scale scientific computing. > > > > Well, for that I would have to know what a TLB is... > > Translation lookaside buffer - a small cache memory for the page table, > which the memory management unit uses to speed up the translation from > virtual addresses to hardware addresses. I guess David wants to write > programs such that they only relatively rarely need to access memory > pages that aren't in the TLB. > This sounds highly system dependent. Do all processors have the same size TLB? I know some current Intel dual core processors have a 16 Megabyte cache, while the roughly equivalent AMD processors have a 2 Megabyte cache. It would seem that cache size and contents could be very important for optimizations at the level one worrys about TLB contents. On the other hand, the AMD dual core processors have up to a 3000 Mts speed while the roughly equivalent Intel processors have a 1600 Mts speed. Both AMD and Intel employ the same instruction sets. Compilers are not likely to recognize differences between processors from the two vendors. Is it common to write scientific programming in such an unportable manner? Jim Rogers