From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM autolearn=unavailable autolearn_force=no version=3.4.4 X-Received: by 10.36.122.69 with SMTP id a66mr7250260itc.24.1494188317670; Sun, 07 May 2017 13:18:37 -0700 (PDT) X-Received: by 10.157.37.213 with SMTP id q79mr1182736ota.11.1494188317642; Sun, 07 May 2017 13:18:37 -0700 (PDT) Path: eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c26no1265473itd.0!news-out.google.com!x200ni784itb.0!nntp.google.com!c26no1265468itd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.ada Date: Sun, 7 May 2017 13:18:37 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:191:8303:2100:5985:2c17:9409:aa9c; posting-account=fdRd8woAAADTIlxCu9FgvDrUK4wPzvy3 NNTP-Posting-Host: 2601:191:8303:2100:5985:2c17:9409:aa9c References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <0fc56bf7-1cfa-4776-9c47-a573db315c5f@googlegroups.com> Subject: Re: Portable memory barrier? From: Robert Eachus Injection-Date: Sun, 07 May 2017 20:18:37 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.ada:46695 Date: 2017-05-07T13:18:37-07:00 List-Id: On Friday, May 5, 2017 at 10:23:45 PM UTC-4, Jere wrote: =20 > Are there any Ada language constructs that can help? No, but you don't need the help you think you need. On modern, superscalar= CPUs, you may have the assignment to the buffer and the index operation oc= curring as part of the same clock cycle. Then the writes (to memory if mem= ory locations are assigned) will occur in the order required by the ISA (fo= r x86, what you require). For some RISC processors a fence will need to occ= ur as part of that bundle of instructions, but trust the compiler for that. If the read of the circular buffer is occurring possibly on a different CPU= core which shares one or more cache levels, the instructions to make a loc= ation Volatile will be ignored by the CPU. The compiler will mark the loca= tion, and the CPU will keep track of the type of memory, but Volatile does = not cause writes to main memory. What will happen instead is that the cache= coherency subsystem will insure that any accesses by CPU cores, GPUs, disk= drives, or whatever will see a virtual location--which can move about--but= all reads and writes will occur in sequence. Didn't you ever wonder why modern CPUs have billions of transistors? It is= to keep things like this straight. By the way, it can be the case that th= e first of two successive writes (with no intervening reads) will be elimin= ated, and/or additional reads may be added. More to the point, if you caus= e an interrupt, the CPU will put that CPU core in some state consistent wit= h memory. Well, where a cache flush will create such a state in memory. W= ithout a cache flush, the CPU only cares that what it sees through the cach= e--and write pipes--is consistent.