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Date: Thu, 10 Aug 2023 06:03:18 -0700 (PDT)
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Subject: SweetAda on NEORV32
From: Gabriele Galeotti <gabriele.galeotti.xyz@gmail.com>
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Hi all.

I=E2=80=99ve created a NEORV32 target platform in SweetAda (https://github.=
com/gabriele-galeotti).

NEORV32 (https://github.com/stnolting/neorv32) is a popular RISC-V SoC impl=
ementation in VHDL, suited for FPGAs.

The setup so far is blatantly primitive and runs under simulation by means =
of GHDL, outputting a welcome message inside the simulated UART console and=
 continuously output the value of the mtime timer.

So far I have no FPGA hardware (besides the time) ready to create a real im=
plementation, so if someone is using NEORV32 on real hardware, and is willi=
ng to test, it will be very interesting to know about a OK/KO flag feedback=
. The current setup needs only UART clocking parameters in the CTRL registe=
r, which I suppose it depends on the actual clock configuration. In the mea=
ntime I will continue to develop things inside the simulated GHDL environme=
nt.

Best regards,
G